STP-H5-Center for High-performance REconfigurable Computing (CHREC) Space Processor (STP-H5 CSP) - 06.20.18

Overview | Description | Applications | Operations | Results | Publications | Imagery

ISS Science for Everyone

Science Objectives for Everyone
The STP-H5-Center for High-performance REconfigurable Computing (CHREC) Space Processor (STP-H5 CSP) investigation studies a miniature space computer for use on CubeSats, SmallSats and other small spacecraft systems. It is designed to tolerate space radiation, which can damage computer systems, and to minimize energy use and cost. Results validate next-generation computer technology that can be used in future small satellites and other NASA missions.
Science Results for Everyone
Information Pending

The following content was provided by Alan George, Ph.D., and is maintained in a database by the ISS Program Science Office.
Experiment Details

OpNom:

Principal Investigator(s)
Gary Crum, M.S., Goddard Space Flight Center, Greenbelt, MD, United States

Co-Investigator(s)/Collaborator(s)
Alan George, Ph.D., University of Florida, Dept of Electrical and Computer Engineering, Gainesville, FL, United States

Developer(s)
NASA Goddard Space Flight Center, Greenbelt, MD, United States
NSF CHREC Center, University of Florida, Gainesville, FL, United States
NSF CHREC Center, Brigham Young University, Provo, UT, United States

Sponsoring Space Agency
National Aeronautics and Space Administration (NASA)

Sponsoring Organization
Technology Demonstration Office (TDO)

Research Benefits
Space Exploration

ISS Expedition Duration
September 2016 - August 2018; -

Expeditions Assigned
49/50,51/52,53/54,55/56,57/58,59/60

Previous Missions
Information Pending

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Experiment Description

Research Overview

  • Modern commercial-off-the-shelf (COTS) processors provide the utmost in performance and energy-efficiency but are susceptible to ionizing radiation in space, whereas radiation-hardened processors are virtually immune to this radiation but are much more expensive, larger, less energy-efficient, and generations behind in speed and functionality.
  • The primary research goal of the STP-H5-Center for High-performance REconfigurable Computing (CHREC) Space Processor (STP-H5 CSP) project is to investigate and evaluate methods by which we can intelligently combine radiation-hardened and COTS components to produce a hybrid computing system which achieves higher computational performance (among other benefits) than an equivalent (and more expensive) entirely radiation-hardened system, and higher reliability than an equivalent all-COTS system.
  • Moreover, the CSP project focuses upon how best to apply a broad array of principles in fault-tolerant computing to augment the inherent reliability of a mixed radiation-hardened and COTS computing solution for varying mission needs.
  • This technology demonstration uses a new approach to space computer design along with new state-of-the-art devices to show that high-performance embedded processors can be reliably developed for lower cost and power consumption.
  • If successful, this research will prove the usefulness of experimental design and fault-tolerant strategies demonstrated in CSP as well as build more confidence in the incorporation of more commercial components and technology in space systems.

Description

Given the nature and purpose of past, present, and future spacecraft, from earth science to space science and exploration to defense surveillance, one of the most critical needs and daunting challenges is on-board computing. This challenge comes in two major areas, compression and/or processing of data from on-board sensors, and processing of data for autonomous-control functions such as landing and docking. In both areas, demands are rapidly accelerating because of technology advances in other areas, and conventional on-board computing technologies are falling behind, in terms of performance required in a harsh space environment with limited size, weight, and power as well as the inherent hazards of radiation effects outside our planet’s atmosphere. Research on the CHREC Space Processor (CSP) takes a multifaceted approach to on-board computing for use in small satellites (CubeSats or NanoSats), a scalable approach that can support spacecraft of all sizes. Working in collaboration with the NASA GSFC SpaceCube team, researchers in the NSF Center for High-Performance and Reconfigurable Computing (CHREC) at Florida and BYU are developing hybrid space computers that feature an innovative combination of three technologies: commercial-off-the-shelf (COTS) devices; radiation-hardened (RadHard) devices; and fault-tolerant computing. Modern COTS processors provide the utmost in performance and energy-efficiency but are susceptible to ionizing radiation in space, whereas RadHard processors are virtually immune to this radiation but are more expensive, larger, less energy-efficient, and generation(s) behind in speed and functionality. By featuring COTS devices to perform the critical data processing, supported by simpler RadHard devices that monitor and manage the COTS devices, and augmented with novel uses of fault-tolerant hardware, software, information, and networking within and between COTS devices, the resulting system can maximize performance and reliability (called performability) while minimizing energy consumption and cost.
 
STP-H5 CSP with CHREC Space Processor (CSPv1), the system architecture is hybrid in nature, featuring a modern, reconfigurable COTS processor with external COTS memory for high-speed and low-power operation, a configurable mix of fault-tolerant computing mechanisms to improve reliability of COTS components, and a set of RadHard components including NAND flash, power circuit, watchdog controller, and reset circuit for reliable operations. The processor architecture is also hybrid in nature, with fixed and reconfigurable logic, featuring the Xilinx Zynq-7020 system-on-chip comprised of dual ARM Cortex-A9/Neon cores, an Artix-7 field-programmable gate array (FPGA) fabric, and supporting IP. Finally, the fault-tolerant architecture consists of authentication for bootstrap from multiple images in flash, error-correction coding on memory, internal and external watchdogs for the processor, and a library of software and hardware objects that can be selectively layered atop the fixed and reconfigurable halves of the Zynq. These architectures are evaluated for and during the mission in terms of performance, reliability, power, and cost as well as initial data on radiation effects.

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Applications

Space Applications
Today’s commercially available computers are efficient and powerful, but they are not designed to work in space, where ionizing radiation can affect their performance. Radiation-hardened computers can work well in space, but are much more expensive, less efficient and larger, which increases mission costs. This investigation studies how off-the-shelf components can be combined with radiation-hardened components to produce a hybrid computer that offers excellent performance, low cost and high efficiency.

Earth Applications
Computers with fault-tolerant technology can continue working even after their chips are interrupted by charged particles. This technology benefits devices used in environments exposed to radiation, including high-altitude aircraft, nuclear reactors, and hospitals. Low-cost, high-performance computers can also benefit development of small unmanned aerial vehicles (UAVs) and other devices.

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Operations

Operational Requirements and Protocols

Operational requirements for CSP include the successful downlink of terrestrial scene image products, high-performance image processing of data products, recording FPGA upset and scrubbing data, recording processor upset rates. The exploration of fault-tolerant computing techniques includes reliable middleware and novel approaches for overhead reduction of fault-tolerant designs, upload of new applications and programs on orbit to extend mission objectives, partial Reconfiguration (PR) of functions and applications, autonomous computing through selection of "good" images with image classification algorithms, use of multiple virtualized accelerators ("contexts") for reduced logic area and improved system and application flexibility. Demonstration of adapting hardware for changing workloads using dynamic and runtime synthesis, use of high-level synthesis and OpenCL system APIs for onboard processing.
 
CSP continuously sends health and status information as well as periodic compressed thumbnail terrestrial images for evaluation and future download. Image products are autonomously screened with image classifiers to block out all-black or completely cloud covered images. Images products can be selectively processed with a variety of image processing techniques including edge enhancement and compression. Ground station sends up commands to: upload new applications, request processing of images, downlink larger resolution images, download logs and experiment files.

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Decadal Survey Recommendations

Information Pending

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Results/More Information

Information Pending

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Related Websites
SpaceCube (TM), A Family of Reconfigurable Hybrid On-Board Science Data Processors
NSF Center for High-Performance Reconfigurable Computing

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Imagery

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NASA Image: ISS050E052652 - Space Test Program-H5 (STP-H5). Photo taken during Expedition 50.

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