A bottom-up approach is developed to integrate vertically aligned carbon nanotubes (CNTs) into nanoscale vertical interconnects, which can conduct much higher currents and enable more layers for Si-based integrated circuit (IC) chips.
Carbon nanotube research may pave ways for smaller, faster computers, networks, and sensors. Computer chips with more layers and smaller components can do more for NASA, which needs high-performance computing in small packages for future autonomous spacecraft. The robustness is also important for applications in high radiation and thermally insulated space environments.
IC interconnects from the bottom up
A big challenge for device fabrication is how to control the placement and orientation of the nanoscale elements. By combining lithography, plasma enhanced chemical vapor deposition (PECVD), and other semiconductor processing techniques, a novel bottom-up approach (Fig. 1) has been demonstrated in NASA Ames Research Center's Center for Nanotechnology to integrate vertically aligned multiwalled carbon nanotubes (MWCNTs) into multilevel interconnects in silicon-based ICs ( Appl. Phys. Lett., 82 (15), pp 2491-2493, 2003). Figure 1. The processing flow of the bottom-up approach.
The processes involve plasma deposition of CNTs, dielectric-electric gap filling, chemical mechanical polishing (CMP), annealing, etc., all compatible with current IC manufacturing practice. MWCNTs retain their integrity and demonstrate electrical properties consistent with their original structure (Fig. 2).
The extraordinary properties of CNTs
A CNT is a long, thin, hexagonal lattice (graphene) of carbon molecules rolled into a tube with a diameter of 1 to ~200 nm and a length over 10 m m (Fig. 3). CNTs display extraordinary mechanical, electrical, and thermal properties. Figure 2. The as-grown (left) and SiO2 encapsulated (right) vertical carbon nanotube array.
They can conduct electricity as well as copper, conduct heat as well as a diamond, and are a hundred times stronger than steel at the same dimension. They may consist of one or more graphitic shells, i.e. single or multi-walled.
High currents, and no grooves required
As copper components get smaller, their resistance to the flow of electricity increases. This obviously stands in the way of making smaller chips. By contrast, CNTs can carry much higher current due to their robustness. Figure 3. The schematic diagram of the atomic structure of a single-walled carbon nanotube.
This property, in addition to their infinitely small size, opens the door to smaller chip configurations. Currently, more than 10 million amperes in a square centimeter area can be passed through a MWCNT continuously over six days without any deterioration. Today's copper interconnects can't match that.
Another problem with today's copper conductors is that one has to create deep, narrow trenches on silicon wafers in which to bury them. This presents an increasingly difficult challenge to manufacturers who want to make components smaller and smaller. The CNT interconnects eliminate this requirement. The requirements for barrier and seed layers for Cu interconnects can be also removed for the new process.
Easy for multilevel integration
Since the final step resulting in a planarized surface (Fig. 4), manufacturers can repeat the whole processes again to build more cake-like layers of electronics on a chip by using vertical carbon nanotube 'wires' to interconnect the layers. Multilevel integration is feasible.
The planarized chip with embedded vertical MWCNTs can be also used for device fabrication. Using localized electrochemical deposition, Ni catalyst particles can be deposited at the very end of first layer MWCNTs. A PECVD can be applied to generate the second layer of vertically aligned CNT structure. A tunneling junction is demonstrated between these two CNT layers. By properly doping each layer, a high-density two-dimensional diode array may be fabricated using this method.
In 1965, just four years after the first planar integrated circuit (IC) was discovered, Gordon Moore observed that the number of transistors per integrated circuit had grown exponentially. He predicted that this would continue, and the media soon began to call his prophesy "Moore's Law." Figure 4. The SEM image at 45∞ perspective angle (Top) and TEM image at the side of CNTs exposed at the SiO2 surface after planarization. The scale bars are 200 nm and 50nm, respectively.
For nearly forty years, Moore's Law has been validated by the technological progress achieved in the semiconductor industry. Now, however, industry experts are warning of a "Red Brick Wall" that, as early as 2007, could block the continued scaling predicted by Moore's Law. The "red bricks" in the wall are those areas of technical challenge for which no known materials and manufacturable solutions exist. One such "brick" is the challenge of finding a new material and processing technology to replace the metals used today to interconnect transistors on a chip.
NASA is also keenly interested in future chip development because we need to develop smaller and more complex computer systems for future space missions. By integrating ultra-small nanostructured materials such as carbon nanotubes into silicon-based ICs, we may invent new techniques that could break through the "Red Brick Wall."